Driver circuits are used in many different applications to transmit a digital signal from a source device to a destination device. They operate by switching a supply current or voltage to control the level and polarity of the transmitted signal.
FIG. 1 illustrates switching of a driver circuit by plotting signal level against time. The signal level denotes the signal passed by a transistor which has been turned on at time To. It will readily be appreciated that the precise values of the high and low signal levels will vary depending on the operating voltage/current of the circuit.
The bold line illustrates a circuit with a symmetric switch-on time and switch-off time. The dotted lines illustrate schematically variations in the switch-on and switch-off times. A rise time Tr is defined as the time taken from 20% of the maximum signal value to 80% of the maximum signal value. Similarly, a fall time Tf is defined as the time taken to drop from 80% of the high signal value to 20% of the high signal value. These times are illustrated in FIG. 1 for the fastest rise time and slowest fall time.
Fast rise and fall times are generally advantageous in a circuit, particularly in the context of digital connectors, such as LVDS (low voltage differential signal) Transmission cables can be subject to a so-called Eye Pattern Test to analyze the quality of a digital signal transmitted by the connector. The eye test is carried out using a tool which provides a sampled version of the signals' oscilloscope display as a mechanism for judging the signals' behavior. An “eye” is defined in the centre of a screen displaying the sampled signal, the eye representing how much space separates ones and zeros in the digital signal to ensure that they do not cross. The more space around the “eye” the better the signal quality. The “eye” is sometimes referred to as a mask or mask region, and for some tests it can take a hexagonal or approximately hexagonal shape. This is referred to herein as a hexagonal eye mask test. Other, similar tests can operate using different shaped “eyes”, for example, a diamond shape. However, the hexagonal eye mask test is considered to be the more demanding.
Generally, the faster the switch time, the higher the quality of the signal and the better the separation between ones and zeros or bit levels in a multi level transmission (MLT) environment.
As the quality of the signal degrades, the sample digital wave present on the display starts to extend into the “eye” which is indicative of a low quality and a high probability that ones and zeros will become confused in the destination device.
However, fast switching of transistors through a load generates electromagnetic interference (EMI) which takes the form of radiating high frequency signal components. The faster the rise and fall times, the greater the EMI.
Therefore, it would useful to provide a circuit with a controlled switching time to improve digital signal quality, while reducing electromagnetic interference.
There have been previous attempts. One attempt is RC slew rate control. FIG. 2 illustrates a switch circuit comprising upper switches 2a, 4a and lower switches 2b, 4b. Numeral 6 denotes a resistive load at a destination device (receiver side) coupled between terminals Y and YZ. Each switch path is associated with a capacitor 8 for slowing down the switch transition in conjunction with the resistor 6, according to an RC delay factor.
The switch circuit shown in FIG. 2 operates as a current mode transmitter to drive differential inputs across the load illustrated in the form of resistor 6. Input signals GP, GN are applied to control switches 2a and 2b. 2a is a switch of a first polarity, for example, implemented with a P-channel CMOS transistor and 2b is a switch of a second polarity, for example, implemented as an N-channel CMOS transistor. The complement signals of GP, GN, are applied to switches 4a and 4b, which are similarly switches of a first and second polarity respectively.
When the input signal GP is negative or logic 0, switch 2a is caused to close and switch 4a is open. Its complement signal GN causes switch 2b to close. This creates a current path through 2a, load 6 and switch 2b through which current supplied by a current source 10 can flow. In this way, a differential voltage indicative of the polarity of GP is developed across the load 6. When the polarity of the input signal GP changes, switch 2a opens and switch 4a closes. The input signal GNB causes switch 4b to close while GN opens switch 2b. Thus, a current path is supplied for current from the current source 10 through switch 4a, load 6 and switch 4b, reversing the polarity of the differential voltage. Terminals Y, YZ are coupled to transmitter wires in a cable or the like for transmitting the current to develop a differential voltage at a destination device.
FIG. 2A shows the effect of differing values for RC, where C is the capacitance of capacitor 8 and the effect of those differing values on the signal characteristics in the “eye” test.
One difficulty with this attempt is that as the value of the capacitor increases to slow down the switch transition times and therefore reduce EMI, so the quality of the digital signal subject to the eye test decreases. Thus there is a limit to the effectiveness that can be obtained using this technique. Moreover, relatively large capacitors are required, and it is difficult to control the characteristics of the circuit across PVT (process, voltage, temperature), because of these capacitors. Where EMI levels remain too high, spread spectrum clocking has been used to reduce their effect on circuitry in the source device/connector.
Another attempt to reduce EMI is described in U.S. Pat. No. 5,917,340 which describes a Twisted Pair current driver implemented in CMOS. The driver circuit is divided into four differential drivers labeled S1 . . . S4 in FIG. 3. Each differential driver has a current source which is a fraction of the total current required to be driven. In U.S. Pat. No. 5,917,340, these current values are all equal, at I/4. Each differential driver takes a pair of differential inputs P0, N0; P1, N1; P2, N2 and P4, N4 respectively. The drivers are coupled in parallel across the twisted pair outputs TP+, TP−. The connections between the drivers are not shown in FIG. 3 for the sake of clarity, but it will be appreciated that the TP+ outputs are coupled together, and TP− outputs are coupled together.
The inputs P1, P2 . . . P4 are all derived from a single positive input P0, while the inputs N1, N2 . . . N4 are all derived from a negative input N0. P0 and N0 are differential inputs, such that when the input P0 is positive, the input N0 is negative and vice versa. The positive inputs P1, P2 . . . P4 are derived from the input P0 by respective delay elements 12, each of which delays activation of the respective driver by an amount td. Similarly, for the negative inputs N1 . . . N4.
This provides a smoothing or “staircase” effect for switching the switches on and off, which is illustrated in FIG. 4. FIG. 4 shows the progressive turning on of the switches responsive to the individual inputs P0, P1 . . . P4 and N0, N1 . . . N4 respectively. The delay td is shown operating between each successive activation. At each successive activation, the level of current driven onto the outputs TP+, TP− increases as shown in the lower graph of FIG. 4 which shows the output current Iout of the twisted pair outputs TP+, TP−.
The limitations of this approach include the consumption of a large area and the requirement for PVT compensated delay elements for finer steps. Further area is wasted for routing of the PVT compensated delay elements.